1995

72-pin SIMM

Approx. 4.25” x 1” 
Has 72 pins on the bottom of the circuit board, 36 on each side.  There is a notch cut in the bottom of the circuit 
board in the middle. These modules measure 4.25 inches long.  Because the notch is not centred they can only 
be put in one way. 

72-pin SIMMs are found in older desktop 486 and Pentium computers. Each 72-pin SIMM provides a 32-bit data 
path, so they can be installed alone in 32-bit systems (486 models) but must be installed in pairs in 64-bit Pentium 
or AMD Athlon systems. 

They are available in FPM or EDO.

INTEL PENTIUM PRO

Socket 8  387 pins

Clock Speed: 133 – 200 MHz
Front Side Bus Speed: 60 – 66 MHz
L1 Cache: 8KB instruction, 8KB data
L2 Cache: 256-1024KB On-Chip.

Manufacturing: 0.35 micron.
Number of Transistors: 5.5 millions

Summary:
The first Intel CPU based on the P6 Micro-architecture. 
The CPU contains on-chip L2 cache in the packaging 
running at core clock-speed. The CPU is intended for 
high end servers/workstations.

INTEL CELERON (Covington)

Clock Speed: 233 – 300 MHz
Front Side Bus Speed: 66 MHz
L1 Cache: 16KB instruction, 16KB data
L2 Cache: None.

Manufacturing: 0.35 micron.
Number of Transistors: 7.5 millions.

Summary:
A stripped down version of the Klamath Pentium II with no 
L2 cache on the Slot 1 module. Unsatisfactory performance.

A special mounting bracket on the motherboard is used to 
secure the Celeron in place in its standard 242-pin 
Slot 1 socket. Intel calls the caseless design SEPP 
(Single Edge Processor Package) to differentiate it from 
the Pentium II SEC (Single Edge Cartridge). Some believe 
that the real purpose for the different mounting configurations 
is to prevent users from placing lower cost processors onto 
Pentium II motherboards.

INTEL CELERON (Mendocino)

Clock Speed: 300A – 533 MHz
Front Side Bus Speed: 66 MHz
L1 Cache: 16KB instruction, 16KB data
L2 Cache: 128 KB full speed On-die.

Manufacturing: 0.25 micron.
Number of Transistors: 19 millions.

Summary:
Similar to Pentium II Deschutes but with integrated on-die 
128 KB cache. Also available in Socket 370 package.

1998

SDRAM 168-pin DIMM

Approx.  5.375” x 1.375
The DIMM is larger than either of the SIMMs.  They contain 168 pins on the bottom of the circuit board.  
There are two notches on the bottom of the board and they must be aligned properly in order for them to 
be inserted.  These memory modules are inserted one at a time unlike the SIMMs, which have to be 
inserted in pairs in 64 bit systems. 

168-pin DIMMs are available in FPM, EDO, PC66, PC100 and PC133. 

The number of chips on a 168-pin DIMM may vary, but they have 84 pins on the front and 84 pins on the 
back for a total of 168.

INTEL PENTIUM II

Slot 1 SECC 242 pin
Single Edge Contact Cartridge

Clock speed: 233 – 450 MHz
Front Side Bus speed: 66 – 100 MHz
L1 Cache: 16KB instruction, 16KB data
L2 Cache: 512KB half-speed cache.

Manufacturing:
0.35 micron “Klamath” (233-300 MHz).
0.25 micron “Deschutes” (300-450 MHz).
Number of Transistors: 7.5 millions

Due to the difficulty in manufacturing the Pentium Pro 
with on-chip L2 cache, Pentium II moved the L2 cache 
to an external cache reside in the “Slot 1” package. L1 
Cache is doubled, and added the MMX instructions. 
100 MHz front side bus is introduced after 350 MHz models.

INTEL PENTIUM III (Katmai)

Slot 1 SECC 242 pin
Single Edge Contact Cartridge

Clock Speed: 450 – 600 MHz
Front Side Bus Speed: 100 – 133 MHz
L1 Cache: 16KB instruction, 16KB data
L2 Cache: 512KB half-speed cache.

Manufacturing: 0.25 micron.
Number of Transistors: 9.5 millions

Summary:
Same as Pentium II with added new SSE SIMD instructions. 
The “B” model introduces 133 MHz front side bus.

INTEL PENTIUM III (Coppermine)

Slot 1 SECC 242 pin
Single Edge Contact Cartridge
And also available in
Socket 370 FC-PGA
Flip Chip Pin Grid Array

Clock Speed: 600 – 1000 MHz
Front Side Bus Speed: 100 – 133 MHz
L1 Cache: 16KB instruction, 16KB data
L2 Cache: 256KB full-speed On-die cache.

Manufacturing: 0.18 micron.
Number of Transistors: 28 millions

Major improvements from the original Pentium III, the L2 
cache is now fully integrated onto the CPU die, and the 
L2 datapath, Associative, and Latency are also improved. 
The later model also revert back to the more 
conventional FC-PGA socket model from Slot 1.

AMD ATHLON K7 (Pluto, Orion)

Slot A 242 pin SECC

Clock Speed: 500 – 1000 MHz
Front Side Bus Speed: 100 MHz double data rate.
L1 Cache: 64KB instruction, 64KB data
L2 Cache: 512KB external cache.

Manufacturing:
0.25 micron (Pluto).
0.18 micron (Orion)
Number of Transistors: 22 millions

The first processor based on the K7 architecture. The L2 
cache is located on the external module similar to 
PII/III(katami) and runs at 1/2,3/5, 1/3 of the core clock speed.

AMD ATHLON K7 (Thunderbird)

Socket A 462 pin

Clock Speed: 650 – 1400 MHz
Front Side Bus Speed: 100/133 MHz double data rate.
L1 Cache: 64KB instruction, 64KB data
L2 Cache: 256KB on-die cache.

Manufacturing:
0.18 micron.
Number of Transistors: 37 millions

Similar to the improvement Intel made with the Coppermine 
core, the thunderbird integrates the L2 cache into the 
processor die and running at full core clock speed. The 
thunderbirds produced in Dresden fab are also the first 
x86 CPU to use the copper-interconnect.

INTEL PENTIUM 4 (Willamette)

Socket 423 and Socket 478

Clock Speed: 1300 – 2000 GHz
Front Side Bus Speed: 100 MHz quad data-rate.
L1 Cache: 12K micro-op instruction, 8KB data
L2 Cache: 256 KB full speed On-die.

Manufacturing: 0.18 micron.
Number of Transistors: 42 millions.

The first CPU core with the new Netburst(P68) architecture. 
Because of the fact that it is still manufactured using the older 
0.18 micron technology. The die of this CPU is extremely large.

AMD ATHLON XP (Palomino)

Socket A 462 pin

Clock Speed: 1333(1500+) – 1.67(2100+) MHz
Front Side Bus Speed: 133 MHz double data rate.
L1 Cache: 64KB instruction, 64KB data
L2 Cache: 256KB on-die cache.

Manufacturing:
0.18 micron.
Number of Transistors: 37.5 millions

The Palomino core is mainly a reworked Thunderbird core to 
reduce power consumption with added thermal diode. The core 
also incorporated the SSE instructions, increased TLB, and a 
data prefetch unit. Externally, the CPU is packaged using the 
OPGA array (ie. Plastic) instead of Ceramic.

2002

DDR SDRAM 184pin - Data is processed twice in each FSB clock cycle.

Approx.  5.375” x 1.375
But what's all the 133/266, 166/333 and 200/400 numbers you ask? And what about 
PC2100, PC2700 and PC3200? What's it all mean? 

If the RAM is quoted as DDR266, then this means the data is running 2 x 133 
where 133 is the core Front Side Bus speed.  

But wait, the RAM says it is PC2100.  What's that?   2100 is a new naming standard for 
speed or throughput of data. It equals the theoretical speed of the RAM in MegaBytes per 
second. Here's a table to help explain:

PC1600 		Data at 200MHz 			Theoretical transfer rate of
DDR200		Clock 200MHz core FSB	 	1.6Gigabyte per second
_________________________________________________________________
PC2100 		Data at 266MHz 			Theoretical transfer rate of 
DDR266		Clock 133MHz core FSB		2.1Gigabyte per second
_________________________________________________________________
PC2700		Data at 333MHz			Theoretical transfer rate of 
DDR333		Clock 166MHz core FSB		2.7Gigabyte per second
_________________________________________________________________
PC3200 		Data at 400MHz			Theoretical transfer rate of  
DDR400	 	Clock 200MHz core FSB	  	3.2 Gigabyte per second

AMD ATHLON XP (Thoroughbred)

Socket A 462 pin

Clock Speed: 1466(1700+) – 2.1(2800+) MMz
Front Side Bus Speed: 133/166 MHz double data rate.
L1 Cache: 64KB instruction, 64KB data
L2 Cache: 256KB on-die cache.

Manufacturing:
0.13 micron.
Number of Transistors: 37.5 millions

Summary:
Simply a die shrunk of the Palomino core to 0.13 micron. 
All the functionalities remains unchanged.

INTEL PENTIUM 4 (Northwood)

Socket 478

Clock Speed: 1600 – 3066 MHz
Front Side Bus Speed: 100 MHz or 133 MHz quad data-rate.
L1 Cache: 12K micro-op instruction, 8KB data
L2 Cache: 512 KB full speed On-die.

Manufacturing: 0.13 micron.
Number of Transistors: 55 millions.

The second CPU based on the Netburst architecture. The 
processor is now manufactured using copper 0.13 micron 
technology. The L2 cache has been double in size to 512KB. 
However, the die size is still smaller than the Willamette.

AMD ATHLON XP (Barton)

Socket A 462 pin

Clock Speed: 2500+ – 3000+ MHz
Front Side Bus Speed: 166 MHz double data rate.
L1 Cache: 64KB instruction, 64KB data
L2 Cache: 512KB on-die cache.

Manufacturing:
0.13 micron.
Number of Transistors: 54.3 millions

Same as Thoroughbred core Athlon XP with an increase L2 
cache to 512KB.

INTEL PENTIUM 4 (Prescott)

Socket 478

Clock Speed: to 3.6GHz
Front Side Bus Speed: 200 MHz quad data-rate.
L1 Cache: 16K
L2 Cache: 1MB full speed On-die.

Manufacturing: 0.09 micron or 90nm.
Number of Transistors: 125 millions.

Didn’t show significant performance improvement over the 
Northwood core despite new micron size and 70 million 
extra transistors.

Later generation Socket 478 Pentium 4 processors were the 
first to implement Intel's Hyper-Threading Technology, which 
allowed for applications to be run in parallel, thus improving 
the performance of the system. Although not nearly as strong,
the concept is similar to having a dual processor system or 
dual-core processor, as systems with Hyper-Threading enabled
processors can handle intensive applications much easier than 
the same system without Hyper-Threading.

INTEL PENTIUM 4 (Grantsdale & Alderwood)

Socket 775

Clock Speed: to 3.6GHz
Front Side Bus Speed: 200 MHz quad data-rate.
L1 Cache: 16K
L2 Cache: 1MB full speed On-die.

Manufacturing: 0.09 micron or 90nm.
Number of Transistors: 125 millions.
New LGA – Land Grid Array socket

The Celerons in Socket T only support a 533 MHz frontside bus 
(Celeron D), and the Pentium 4s support both an 800 MHz 
frontside bus and a new 1066 MHz (266 MHz x 4) frontside bus. 
Speeds of the processors can range from under 3 GHz

AMD ATHLON SEMPRON (ClawHammer)

Socket 754 pin  64Bit

Clock Speed: SP 3100+ / 1.80GHz
Front Side Bus Speed: 166 MHz double data rate.
L1 Cache: 64KB instruction, 64KB data
L2 Cache: 256KB on-die cache.

Manufacturing:
0.13 micron.
Number of Transistors: 68.5 million 

This socket is the cheap socket for 64 bit Athlons. 
Motherboards with this socket only support single 
channel memory configurations which will slow 
down performance.

AMD ATHLON 64 (939 Pin) (SledgeHammer)
AMD ATHON FX (940 Pin) (Opteron)

Socket 939 pin  64 Bit/32 Bit

Clock Speed: 3500+ / 2.20GHz
Front Side Bus Speed: 200 MHz quad-data rate with 
Hyper Transport (Effective 1600MHz FSB).
L1 Cache: 64KB instruction, 64KB data
L2 Cache: up to 1024KB on-die cache.

Manufacturing:
0.13 micron.
Number of Transistors: 105.9 million transistors 

INTEL PENTIUM D (Smithfield - Dual Core)

Socket 775 LGA

Clock Speed: to 2.8 - 3.2 GHz
Front Side Bus Speed: 233 MHz quad data-rate.
L1 Cache: 16K
L2 Cache: 2x1MB full speed On-die.

Manufacturing: 0.09 micron or 90nm.
Number of Transistors: 230 millions.

Does work in existing socket 775 motherboards. Clocks 
have reached a temporary ceiling.  Dual channel and 
multiple data rates are the existing future.

Dual Core, Dual Channel, Hyper Threading, 
Hyper Transport, Pipelines - All using more channels for
moving data about without increasing clock speeds.

AMD 64 x2 (Winchester - Dual Core)

Socket 939 pin  64 Bit/32 Bit

Clock Speed: 4500+ 
Front Side Bus Speed: 200 MHz quad-data rate with 
Hyper Transport (Effective 1600MHz FSB).
L1 Cache: 64KB instruction, 64KB data
L2 Cache: up to 2x1024KB on-die cache.

Manufacturing:
0.09 micron or 90nm.
Number of Transistors: 233.2 million transistors 

DDR2 SDRAM 240pin - Data is processed four times in each FSB core clock cycle effectively Quad Data Rate.

Approx.  5.375” x 1.375
The advantage of DDR2 over DDR SDRAM is the ability for much higher clock speeds, due to design improvements.

The difference of DDR2 to DDR is a doubled bus frequency for the same physical clock rate, thus doubling the effective 
data rate another time.

PC2-3200 		Data at 400MHz 			Theoretical transfer rate of
DDR200x2		Clock 100MHz core FSB	 3.2 Gigabyte per second
_________________________________________________________________
PC2-4200		Data at 533MHz 			Theoretical transfer rate of 
DDR266x2		Clock 133MHz core FSB	4.267 Gigabyte per second
_________________________________________________________________
PC2-5300		Data at 667MHz			Theoretical transfer rate of 
DDR333x2		Clock 166MHz core FSB	5.333 Gigabyte per second
_________________________________________________________________
PC2-6400 		Data at 800MHz			Theoretical transfer rate of  
DDR400x2	 	Clock 200MHz core FSB	  6.4 Gigabyte per second

DDR2 DIMMs are not backwards compatible with DDR DIMMs. The notch on DDR2 DIMMs is in a different position 
than DDR DIMMs, and the pin density is slightly higher than DDR DIMMs. DDR2 is a 240-pin module, DDR is a 184-pin module

Current Range of INTEL and AMD Dual Core

Intel Core 2 Duo  	 

2008

DDR3 SDRAM 240pin

Approx.  5.375” x 1.375
DDR3 modules can transfer data at the effective clock rate  of 800–1600 MHz using both rising and falling edges of a 
400–800 MHz I/O clock. In comparison, DDR2's current range of effective data transfer rate is 400–800 MHz 
using a 200–400 MHz I/O clock, and DDR's range is 200–400 MHz based on a 100–200 MHz I/O clock. To date, 
the graphics card market has been the driver of such bandwidth requirements, where fast data transfer 
between framebuffers is required.